On September 10, ESWIN Computing held the first Developer Partners Conference (ESWIN Computing DPC 2024) in Beijing E-town. Themed “Green, Open, Fusion,” the conference spanned key topics such as technological innovation, product application, and ecosystem building. It extended an invitation for collaboration to developers, industry partners, and other stakeholders to accelerate the integration and application of RISC-V across various industries and promote ecosystem innovation and industry progress of the new-generation RISC-V digital infrastructure.
ESWIN Computing Developer Partners Conference 2024
A cohort of prestigious experts, scholars, and entrepreneurs addressed the conference, sharing their views on the development opportunities of RISC-V in the AI era. They included: Ni Guangnan, member of the Chinese Academy of Engineering; Wu Hanming, member of the Chinese Academy of Engineering; Calista Redmond, CEO of RISC-V International; Yunsup Lee, co-founder and Chief Technology Officer of SiFive; Xie Tao, Chair Professor at Peking University and Artificial Intelligence and Machine Learning Technical Committee of RISC-V International; and Bao Yungang, chief scientist at Beijing Institute of Open Source Chip.
RISC-V Digital Infrastructure: Green, Open, Fusion
As the Fourth Industrial Revolution is underway, we now stand on the brink of the AI era. The rise and application of large language models have fueled an exponential growth in computing power, posing significant challenges for digital infrastructure such as high energy consumption, insufficient innovation vitality, and high costs of system implementation. What kind of digital infrastructure and industrial innovation system can meet the needs of the AI era?
In his keynote speech titled “RISC-V Digital Infrastructure: Green, Open, Fusion,” Wang Dongsheng, Chairman of ESWIN Computing, shared his profound insights, stating “Green, open, and fusion point the way for addressing these challenges, unlocking new market opportunities and fostering a new industrial innovation framework. RISC-V, designed for the AI era, is the computing architecture that aligns perfectly with the principles of green, open, and fusion.
Wang Dongsheng, Chairman of ESWIN Computing, delivers a keynote speech
He then elaborated that “green” refers to the goal of achieving high energy efficiency by driving the iteration and upgrade of algorithms, architectures, and processes in the AI era, so the “artificial intelligence system” of digital infrastructure can be as energy-efficient as human brain to meet the needs of sustainable development. “Open” means fostering an open mindset, open standards, open scenarios, and open cooperation. This includes encouraging more industry partners to engage in the innovation and creation of the new generation of digital infrastructure and jointly promote ecosystem prosperity and industrial innovation. “Fusion” entails efforts to build a universal computing base suited to different fields and scenarios, advance the fusion of heterogeneous computing, enhance the compatibility of software and algorithms and the efficiency of resource scheduling, and reduce the complexity and cost of system implementation, thereby improving the overall input-output ratio and cost-performance ratio of systems.
Ni Guangnan remarked that the concept of RISC-V Digital Infrastructure (RDI) proposed by Chairman Wang Dongsheng will be the catalyst for building the RISC-V ecosystem and industry. The perfect fusion of RISC-V and chiplets will propel innovation and transformation of computing architectures in the field of domain specific architecture (DSA). This, coupled with software optimization, is poised to usher in a new era where “hardware is defined by demand.”
Ni Guangnan, member of the Chinese Academy of Engineering, delivers a speech
Wu Hanming pointed out that new quality productive forces emphasize the use of advanced technologies and innovative models of new-generation digital infrastructure to increase the production efficiency and create value in the age of information, digitalization, and intelligence. The concept of RDI is a vivid example that aligns with this vision. It advocates for close collaboration among all levels of the ecosystem to drive the innovation and development of digital infrastructure.
Wu Hanming, member of the Chinese Academy of Engineering, gives a speech
RISC-V stands out with its openness, high efficiency, flexibility, low power consumption, modular design, and scalability, charting a unique course of development distinct from the closed x86 and the licensed ARM models. It has revealed to the industry the potential for architectural innovation through a simpler approach. From embedded systems to the IoT and from edge computing to server applications, RISC-V is finding its way into every corner of the digital infrastructure landscape, emerging as a key element in developing a universal computing base for the AI era.
RISAA technology and ecosystem platform unveiled
According to a report released by the leading consultancy SHD Group, annual shipments of RISC-V chipsets totaled 1.3 billion in 2023 and are expected to reach 16.2 billion by 2030, with a compound annual growth rate of over 44%. In a span of just a decade, RISC-V has accomplished what traditional architectures have done over three decades, showcasing its extraordinary competitiveness across a diverse range of fields.
“RISC-V has now reached a pivotal moment in its development: it's time to build upon our achievements in the IoT sector and start bringing RISC-V to strong ecosystem domains.” Dr. He Ning, Senior Vice President and Chief Technology Officer of ESWIN Computing said, “The concept of RDI proposed by Chairman Wang Dongsheng carries special relevance. It integrates the relatively abstract concept of RISC-V into the concrete entity of digital infrastructure, consolidating scattered, unscalable, and unsystematic RISC-V products into a complete system. Furthermore, it concisely encapsulates the responsibility and mission of RISC-V in the building of a digital China.
RDI refers to all kinds of digital infrastructure that adopts the RISC-V architecture, including chips, devices, software, systems, and the resulting “new computing power, new networks, new data, new facilities, and new terminals.” Vertical industry scenarios will be the primary breakthrough point for the implementation of RDI. To swiftly develop innovative solutions tailored to various industry specific scenarios and increase the adoption of RISC-V requires extensive, in-depth, and ongoing cooperation throughout the supply chain.
At ESWIN Computing DPC 2024, Dr. He Ning announced the release of the RISC-V+AI Architecture (RISAA) platform designed to facilitate the implementation of RDI. He stated, “We believe that RISC-V will eventually become the native architecture for AI, and new terminals and devices empowered by AI will be the killer applications for RISC-V. Therefore, the combination of RISC-V and AI is both a trend and a certainty. The RISAA platform is a green computing platform built on the new generation of computing architectures in the AI era. RISAA is not just a technical support platform; it is also an ecosystem collaboration platform aimed at promoting industrial application. It is dedicated to addressing common challenges faced by enterprises in the development and promotion of RISC-V products and ecosystems. ESWIN Computing hopes to leverage the RISAA platform to facilitate technical cooperation, application implementation, and ecosystem building among industry partners. As generative AI is reshaping the industrial ecosystem and new applications and demands are rapidly emerging, we must pool strengths to accelerate the iteration of technologies, products, and software ecosystems. Only in this way can we seize the golden period for RISC-V.”
He Ning, Senior Vice President and Chief Technology Officer of ESWIN Computing, announces the release of RISAA
The RISAA platform encompasses three underlying technical capabilities and a five-tiered industrial ecosystem collaboration model.
The three underlying technical capabilities are as follows: 1. RISC-V+AI technology base: which aims to build a universal computing base that is compatible with various computational requirements; 2. domain specific computing (DSC) capability: which aims to enhance the competitiveness of RISC-V products in various application fields and support the implementation of industry specific scenarios; and (3) open software and hardware interfaces and platform: which are designed to lay the groundwork for technical Interoperability among ecosystem partners.
The five-tiered industrial ecosystem collaboration model requires ecosystem partners to collaborate on innovation and pursue common prosperity at the IP, chiplet, chip, board, and system equipment levels. By integrating technical capabilities at these levels, ESWIN Computing seeks to collaborate with partners to build a RISC-V product matrix and bring RISC-V to high-value markets and strong ecosystem domains.
Cooperation signings for the first batch of RDI ecosystem partners were held at the conference. ESWIN Computing signed strategic cooperation agreements with a number of industry chain partners regarding the adoption of RDI in finance, energy, healthcare, industry, education, smart city, smart home, auto, and other fields. These partners included National Financial Technology Certification Center (Beijing), Zhuhai Huafa Group Co., Ltd., Neusoft Corporation, Wuhan Jingce Electronic Group, BOE Art Cloud, Beijing Yizhuang Smart City Research Institute Group Co., Ltd., and Beijing Zentraedi Intelligent Information Technology Co., Ltd.
Calista Redmond, CEO of RISC-V International, noted the enormous potential of RISC-V + AI in numerous computational scenarios. Based on the platform ESWIN Computing, she called on global industry peers to continue driving the development of the ecosystem, contribute to open-source software, actively tap supply chains, market opportunities, and uncharted frontiers, and propel industry progress through innovation.
Calista Redmond, CEO of RISC-V International, gives a speech
Innovative chips and solutions tailored for smart devices, smart automotive, and intelligent computing
Founded in 2019, ESWIN Computing positions itself as a “next-generation computing architecture IC and solution provider.” Focusing on display interaction, computing, and connection, the company has built the RISC-V+AI core technology base and RISC-V DSC capabilities. It provides customers with innovative IC products and solutions mainly in three fields: smart terminals, smart vehicles, and smart computing.
At the conference, Lou Xiaodong, Senior Vice President, Chief Product Officer, and CEO of the Computing Business Group of ESWIN Computing, released a number of world-first RISC-V chip products and solutions, which are suitable for smart devices, smart automotive, and intelligent computing scenarios.
Lou Xiaodong, Senior Vice President, Chief Product Officer,
and CEO of the Computing Business Group of ESWIN Computing, announces the release of new products
In the field of smart devices, ESWIN Computing launched the 64-bit RISC-V multimedia SoC compliant with the RVA23 specification, RISC-V esports monitor master control chip, and RISC-V 5G small cell radio frequency transceiver chip.
ICs and solutions in the field of smart devices
As to smart automotive, the company introduced the RISC-V+AI MCU, RISC-V C-V2X SoC, RISC-V automotive ISP, ultra-low latency camera monitor systems (CMS), and flexible OLED smart interaction solution.
ICs and solutions in the field of smart automotive
In the field of intelligent computing, the company unveiled the 64-bit RISC-V Dual-Die AI SoC, high-performance RISC-V development board, smart edge station, 1U MicroServer, and AI accelerator card/video transcoding card Among them, the AI SoC EIC7702X features an 8-core 64-bit out-of-order RISC-V high-performance processor and a self-developed efficient neural network processing unit (NPU). It supports full-stack floating-point arithmetic calculations to accelerate large generative models, and also supports a rich set of extension interfaces, enabling high adaptability for AI smart devices. The product boasts powerful audio and video processing capabilities. It supports video codecs such as H.264 and H.265, and audio codecs including AAC-LC, G.711, and G.722.1; up to 8K@100fps video decoding and 8K@50fps video encoding. Plus, it has up to 4Gbps low-latency Ethernet networking capabilities, offer computing power of up to 40 TOPS at INT8 precision, enabling it to sustain rapidly changing AI workloads and localized AI deployment. The EIC7702X achieved a remarkable score of 8.57/GHz in the SPEC2006 standard test.
ICs and solutions in the field of intelligent computing
ESWIN Computing also announced the development of an open IO HUB heterogeneous chiplet interconnect platform. This platform supports flexible interconnect of various computational chiplets such as GPU, DPU, NPU, and xPU, enabling the expansion of general-purpose compute capabilities, network capabilities, and other compute resources and the application in diverse scenarios. The IO HUB chiplet interconnect platform uses Universal Chiplet Interconnect Express (UCIe) as the interface, enabling high-bandwidth interconnection with third-party chiplets. It supports high-performance DDR4/5 memory and high-speed interfaces such as PCIe 5.0/CXL 2.0, as well as 00G/200G/400G Ethernet. The platform is equipped with an integrated GPGPU accelerator, offering general-purpose hardware acceleration capabilities for network offloading, compression, and decompression. Additionally, it features a high-performance encryption and decryption security engine, guaranteeing high security for products.
On the basis of the IO HUB, chiplets from different vendors can be interconnected to develop computing SoCs tailored to different scenarios. For instance, encapsulating the IO HUB chiplets with computational chiplets through a system in package (SiP) offers general-purpose computing capabilities that can be used in digital infrastructure for cloud computing servers, enterprise computing servers, and other RISC-V digital infrastructure. By encapsulating GPU, NPU, and DPU chiplets, the resulting chips can be used in cloud training and inference servers, edge inference servers, storage servers, network offload computing servers, and more.
According to Lou Xiaodong, ESWIN Computing offers an open IO HUB heterogeneous chiplet interconnect platform and flexible business models, and looks forward to collaborating with chiplet and server vendors to accelerate chiplet interconnect, the adaptation and certification process of chip products, and better meet the needs of end customers for RDI. This will create win-win situations for all.
In the AI era, innovation and industrial development of the RDI ecosystem is an inevitable trend and also a shared opportunity for industry partners. Green computing, open cooperation, and fusion delivers shared value. ESWIN Computing looks forward to more industry partners engaging in the building of the RDI ecosystem. By collaborating and innovating together, we can bring RISC-V to the fore, build a strong RDI ecosystem, and prosper the RDI industry in the AI era.
