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E200
E200
RISC-V 32-bit Architecture IPs
E200:
ESWIN Computing E200 32-bit general-purpose microprocessor is a low-power, high-performance 32-bit RISC-V embedded CPU IP product.
Designed for lightweight embedded microcontrollers, E200 delivers enhanced performance through L1 cache, B extension, F extension, Zicbom extension (cache-block management operations), and Smepmp extension for enhanced security.
Designed for lightweight embedded microcontrollers, E200 delivers enhanced performance through L1 cache, B extension, F extension, Zicbom extension (cache-block management operations), and Smepmp extension for enhanced security.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit IMAC(B)(F) | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | Supports Smepmp, with 0 to 16 PMP regions configurable Supports PPMA (Programmable Physical Memory Attributes) checks | ||||
| Pipeline | 2-stage pipeline | ||||
| TIM | TIM0 and TIM1: configurable size from 0KB to 128MB; ECC optional | ||||
| L1 I$ | Configurable size from 4KB to 128KB; Parity/ECC optional | ||||
| L1 D$ | Configurable size from 4KB to 128KB; Parity/ECC optional | ||||
| Interrupt | Core Local Interrupt Controller (CLIC): supports up to 112 interrupt requests and non-maskable interrupt (NMI) | ||||
| Debug | Debug module: supports JTAG/cJTAG | ||||
| Bus Interface | 1.ICache Port: 32-bit AHB master interface 2.DCache Port: 32-bit AHB master interface 3.ICache Port and DCache Port can be combined into one System Port: 32-bit AHB master interface 4.Peripheral Port: 32-bit AHB master interface 5.Front Port: 32-bit AHB slave interface, used for external access to TIMs |
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| CoreMark （CoreMarks/MHz） | 4.65 | ||||
| Dhrystone-Legal （DMIPS/MHz） | 1.90 | ||||
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