RISC-V CPU IPs
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S500A
S500A
RISC-V 64-bit Architecture IPs
S500A:
ESWIN S500A is an energy-efficient 64-bit RISC-V CPU IP for Functional Safety, which meets ASIL-B functional safety standards compared to S500.

It integrates self-developed 9-stage pipeline, dual-issue and in-order architecture. It supports 3 level of cache, multicores and SMP. A core cluster can have up to 8 cores inside.

The trusted execution environment is supported to meet the system security requirements.

The optional E-Trace/N-Tace for advanced debugging function is supported.

It also supports ECC protection to meet hardware security requirements.

S500A enables running Linux and various operating systems that require MMU support. With the characteristics of high energy efficiency and extensive application fields. It can be applied to AIoT edge computing, network devices and baseband communication, etc.
S500A
Features
Features Description
ISA RV64 GCB(V)
Multi-core dual core, 4 core, 6 core, 8 core option available
Modes Machine-Mode, Supervisor-Mode, User-Mode
Security supporting ESWIN TEE solutions, with up to 64 PMP regions
Pipelines 9-stage superscalar in-order pipeline, 2-way decode
Branch Predictors L0_BTB, BTB, IJTB,BHT, RAS, Loop Buffer
L1 I$ configurable sizes from 8KB to 64KB, ECC optional
L1 D$ configurable sizes from 8KB to 64KB, ECC optional
Private L2$ configurable sizes from 128KB to 512KB, ECC optional
Cluster LLC configurable sizes from 512KB to 4MB, ECC optional
MMU SV39, ITLB, DTLB
Interrupt CLINT, PLIC
Debug Debug module, supporting JTAG
Trace module, supporting standard E-Trace of RISC-V
Bus Interface 1. Memory Port: 128–bit AXI master interface
2. Peripheral Port: 128-bit AXI master interface
3. Front Port: 128-bit AXI slave interface