Home
> RISC-V Technologies
> RISC-V
CPU
IPs
> RISC-V 32-bit Architecture IPs
>
ES000
ES000
RISC-V 32-bit Architecture IPs
ES000:
ESWIN ES000 is a 32-bit RISC-V security CPU IP, specially designed for high security fields such as SIM cards, IoT security, and financial payment.
It implements more than ten Anti-tamper security mechanisms against various side channel attacks.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state, registers and events of the CPU.
It implements more than ten Anti-tamper security mechanisms against various side channel attacks.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state, registers and events of the CPU.
Features
| Features | Description | ||||
| ISA | RV32 E(M)_Zicsr_Zifencei_Zc_Zicon | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | supporting Smepmp, and flexible configuration for 0-16 PMP regions; supporting more than ten security features such as random polarization of data paths and consistent instruction cycles |
||||
| Pipeline | 2-stage pipeline | ||||
| TIM | TIM0 and TIM1, with configurable sizes from 0KB to 128MB, Parity/ECC optional | ||||
| Interrupt | CLIC interrupt controller, supporting up to 112 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module, supporting for JTAG/cJTAG | ||||
| Bus Interface | 1. Peripheral Port: 32-bit AHB master interface 2. System Port: 32-bit AHB master interface (optional) 3. Front Port: 32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
||||
| CoreMark（CoreMarks/MHz） | 2.50 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 1.00 | ||||
