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ES000
ES000
RISC-V 32-bit Architecture IPs
ES000:
ESWIN Computing ES000 32-bit information security processor is a 32-bit RISC-V security CPU IP product with ultra-low power consumption and high security, which is specially designed for high security fields such as SIM cards, IoT security and financial payments.
It implements more than ten Anti-tamper security mechanisms against various side channel attacks.
To ease user RTL simulation debugging, it provides an ESWIN Sight function to let users easily probe the internal state, registers and events.
It implements more than ten Anti-tamper security mechanisms against various side channel attacks.
To ease user RTL simulation debugging, it provides an ESWIN Sight function to let users easily probe the internal state, registers and events.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit EMC/Zc_Zicsr_Zifencei | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | Supporting Smepmp, PMP Region can optional from 0 to 16. Supporting more than ten security features such as random polarization of data paths and consistent instruction cycles. |
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| Pipeline | 2-stage pipeline | ||||
| TIM | TIM0 and TIM1,with configurable sizes from 0KB to 128MB , Parity/ECC optional | ||||
| Interrupt | CLIC interrupt controller, supports 112 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module, supports JTAG/cJTAG | ||||
| Bus Interface | 1. Peripheral Port: 32-bit AHB master interface 2.System Port: 32-bit AHB master interface(Optional) 3. Front port: 32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
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| CoreMark（CoreMarks/MHz） | 2.15 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 0.87 | ||||
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