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R500A
R500A
RISC-V 32-bit Architecture IPs
R500A:
ESWIN Computing R500A 32-bit functional-safety processor is a high-performance 32-bit RISC-V automotive grade real-time CPU IP product with ISO-26262 automotive functional safety ASIL-B level certification.
Support the RV32GCBP instruction set, including official extensions such as Zfh (semi precision floating-point), Zicobom (cache operation), Zicond (conditional execution), Zicsr (CSR read and write), Zience (fetch barrier), SmePMP (enhanced address protection), SPMP (supervised mode address protection), SBA (system mainline access), etc.
Support functions such as PPMA (Programmable Address Attribute Check), Stack Monitor, ESWIN Sight (Internal Signal Insight), N-Trace (Instruction Flow Tracking), etc.
Supports cache consistency feature that allows external devices to access DCache through Front Port to meet the functional requirements for cache consistency in some scenarios.
Supports multiple functional safety mechanisms: register parity check, bus interface protection, SRAM interface protection, and non-safety module isolation.
It can run various real-time operating systems such as FreeRTOS and μClinux, and is also compatible with Linux operating systems that support SPMP.
Suitable for designs with high requirements for interrupt processing speed, such as industrial control, medical device control, storage device control, modem, 5G communication, streaming media transmission, etc., especially suitable for in vehicle ECU/DCU and automotive grade IC design fields.
Support the RV32GCBP instruction set, including official extensions such as Zfh (semi precision floating-point), Zicobom (cache operation), Zicond (conditional execution), Zicsr (CSR read and write), Zience (fetch barrier), SmePMP (enhanced address protection), SPMP (supervised mode address protection), SBA (system mainline access), etc.
Support functions such as PPMA (Programmable Address Attribute Check), Stack Monitor, ESWIN Sight (Internal Signal Insight), N-Trace (Instruction Flow Tracking), etc.
Supports cache consistency feature that allows external devices to access DCache through Front Port to meet the functional requirements for cache consistency in some scenarios.
Supports multiple functional safety mechanisms: register parity check, bus interface protection, SRAM interface protection, and non-safety module isolation.
It can run various real-time operating systems such as FreeRTOS and μClinux, and is also compatible with Linux operating systems that support SPMP.
Suitable for designs with high requirements for interrupt processing speed, such as industrial control, medical device control, storage device control, modem, 5G communication, streaming media transmission, etc., especially suitable for in vehicle ECU/DCU and automotive grade IC design fields.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit IMAC(B)(FDZfh)(P)_Zicsr_Zifencei_Zicbom_(Zicond) | ||||
| Pipeline | 6-stage superscalar in-order pipeline with Branch Predictor | ||||
| Modes | Machine-mode, Supervisor-mode, User-mode | ||||
| Security | PMP region can reach up to 16, supporting PPMA SPMP region can reach up to 16 |
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| TIM | ITIM and DTIM, with configurable sizes from 0KB to 16MB, ECC optional | ||||
| DTIM | ITIM and DTIM, with configurable sizes from 0KB to 16MB, ECC optional | ||||
| L1 I$ | Configurable size (0KB-128KB), 2-way set-associative, 32-byte Cacheline, ECC optional | ||||
| L1 D$ | Configurable size (0KB-128KB), 4-way set-associative, 32-byte Cacheline, ECC optional | ||||
| Interrupt | CLIC interrupt controller, supports up to 1008 fast interrupt requests and recoverable non-maskable interrupt (NMI) | ||||
| FPU | Supports RISC-V Zfh half-precision, single-precision and double-precision floating-point | ||||
| DSP | Supports SIMD (Single Instruction Multiple Data) instruction, supports full RV32P | ||||
| Debug | Debug module: supports JTAG/cJTAG and SBA（System Bus Access Port) Trace module: supports RISC-V N-Trace |
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| Bus Interface | 1. Flash Port: 64-bit read-only AXI master interface 2.Memory Port:64-bit AXI master interface 3.Peripheral Port:32-bit AHB master interface 4.Front Port:64-bit AXI slave interface, used for external access to ITIM , DTIM and DCache |
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| CoreMark（CoreMarks/MHz） | 5.79 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 2.55 | ||||
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