RISC-V Technologies
RISC-V 32-bit Architecture IPs
RISC-V 32-bit Architecture IPs
ESWIN R500A is a 32-bit real-time automotive-grade RISC-V CPU IP with ISO-26262 ASIL-B level automotive functional safety certification.

It supports the RV32GCBP instruction set, including official extensions such as Zfh (semi precision floating-point), Zicobom (cache operation), Zicond (conditional execution), Zicsr (CSR read and write), Zience (fetch barrier), SmePMP (enhanced address protection), SPMP (supervised mode address protection), SBA (system mainline access), etc.

Additional features includes PPMA (Programmable Address Attribute Check), Cache Prefetch, CCP (Cache Coherent Interface), Stack Monitor, ESWIN Sight (Internal Signal Insight), N-Trace (Instruction Flow Tracking), etc.

It can run various real-time operating systems such as FreeRTOS and μClinux, and is also compatible with Linux operating systems that support SPMP.

It suitable for applications with high requirements for interrupt processing speed, such as industrial control, medical device control, storage device control, modem, 5G communication, streaming media transmission, etc., especially suitable for automotive applications such as ECU/DCU/IC design fields.
Features Description
ISA RV32 IMA(FD)C(B)(P)_Zicsr_Zifencei_Zicbom_Zicond_(Zfh)
Modes Machine-mode, Supervisor-mode, User-mode
Security configuration up to 16 PMP regions and up to 64 SPMP regions
Pipeline 6-stage superscalar in-order pipeline,with Branch Predictor
ITIM configurable sizes from 0KB to128MB, ECC optional
DTIM configurable sizes from 0KB to128MB, ECC optional
L1 I$ configurable sizes from 4KB to128KB, ECC optional
L1 D$ configurable sizes from 4KB to128KB, ECC optional
FPU supporting RISC-V Zfh half-precision, single-precision and double-precision floating-point
DSP supports SIMD (Single Instruction Multiple Data) instruction, and full RV32P
Interrupt CLIC interrupt controller, supports up to 1008 fast interrupt requests and non-maskable interrupt (NMI)
Debug Debug module: supports JTAG/cJTAG and SBA(System Bus Access Port)
Trace module: supports RISC-V N-Trace
Bus Interface 1. Memory Port: 64-bit AXI master interface
2. Peripheral Port: 32-bit AHB master interface
3. Front Port: 64-bit AXI slave interface, used for external access to ITIM and DTIM
4. I/O Coherent Port(CCP Port) : 64-bit AXI slave interface used for I/O coherent