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E330A
E330A
RISC-V 32-bit Architecture IPs
E330A:
ESWIN E330A is a 32-bit RISC-V automotive-grade CPU IP.
Based on E330, functional safety mechanism such as Parity/ECC, Stack Pointer Monitor (SPM) and dual-core lock-step function were added to meet ASIL-D functional safety standards.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state, registers and events of the CPU.
Based on E330, functional safety mechanism such as Parity/ECC, Stack Pointer Monitor (SPM) and dual-core lock-step function were added to meet ASIL-D functional safety standards.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state, registers and events of the CPU.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit IMA(FD)CB(P)_Zicsr_Zifencei_Zicbom_(Zicond) | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | supporting Smepmp, and flexible configuration for 0-16 PMP regions | ||||
| Pipeline | 6-stage superscalar in-order pipeline with Branch Predictor | ||||
| TIM | ITIM and DTIM, with configurable sizes from 0KB to 128MB, Parity/ECC optional | ||||
| L1 I$ | configurable sizes from 4KB to 128KB, Parity/ECC optional | ||||
| L1 D$ | configurable sizes from 4KB to 128KB, Parity/ECC optional | ||||
| Interrupt | CLIC interrupt controller, supporting up to 496 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module, supporting JTAG/cJTAG Trace module, supporting RISC-V N-Trace |
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| Bus Interface | 1. Memory Port: 64-bit AHB/AXI master interface 2. Peripheral Port: 32-bit AHB master interface 3. Front Port: 32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
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| CoreMark（CoreMarks/MHz） | 5.26 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 2.89 | ||||
