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E320A
E320A
RISC-V 32-bit Architecture IPs
E320A:
ESWIN E320A is a 32-bit RISC-V automotive-grade CPU IP.
Based on E320, functional mechanism such as Parity/ECC and Stack Pointer Monitor (SPM) are added to meet ASIL-B functional safety standards.
Based on E320, functional mechanism such as Parity/ECC and Stack Pointer Monitor (SPM) are added to meet ASIL-B functional safety standards.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit IMACB(F)(P)_Zicsr_Zifencei_Zicbom | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | supporting Smepmp, and flexible configuration for 0-16 PMP regions | ||||
| Pipeline | 3-stage pipeline | ||||
| TIM | TIM0 and TIM1, with configurable sizes from 0KB to 128MB, and optional Parity/ECC | ||||
| L1 I$ | configurable sizes from 4KB to 128KB, Parity/ECC optional | ||||
| L1 D$ | configurable sizes from 4KB to 128KB, Parity/ECC optional | ||||
| Interrupt | CLIC interrupt controller, supporting up to 496 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module, supporting JTAG/cJTAG Trace module, supporting RISC-V N-Trace |
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| Bus Interface | 1. ICache Port: 32-bit AHB-Lite master interface 2. Dcache Port: 32-bit AHB-Lite master interface 3. Peripheral Port: 32-bit AHB-Lite master interface 4. Front Port: 32-bit AHB-Lite slave interface |
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| CoreMark（CoreMarks/MHz） | 4.10 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 1.98 | ||||
