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E320A
E320A
RISC-V 32-bit Architecture IPs
E320A:
ESWIN Computing E320A 32-bit functional-safety processor is a 32-bit RISC-V automotive grade CPU IP product with low power consumption and high-performance.

Based on E320, functional safety mechanism, such as Parity/ECC, SPM (Stack Pointer Monitor) to meet ASIL-B functional safety standards.
E320A
Features
Features Description
ISA RISC-V 32-bit IMAC(B)(F)(P)_Zicsr_Zifencei_Zicbom
Modes Machine-mode, User-mode
Security Supporting Smepmp, PMP Region can optional from 0 to 16
Pipeline 3-stage pipeline
TIM TIM0 and TIM1,with configurable sizes from 0KB to 128MB, ECC optional
L1 I$ Size configurable from 4KB to 128KB. Parity/ECC optional
L1 D$ Size configurable from 4KB to 128KB. Parity/ECC optional
Interrupt CLIC interrupt controller, supports 496 interrupt requests and non-maskable interrupt(NMI)
Debug Debug module: supports JTAG/cJTAG
Trace module: supports RISC-V N-Trace
Bus Interface 1. 1.ICache Port: 32-bit AHB-Lite master interface
2. 2.Dcache Port: 32-bit AHB-Lite master interface
3. 3.Peripheral Port: 32-bit AHB-Lite master interface
4. Front Port: 32-bit AHB-Lite slave interface
CoreMark(CoreMarks/MHz) 4.45
Dhrystone-Legla(DMIPS/MHz) 1.74