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E302A
E302A
RISC-V 32-bit Architecture IPs
E302A:
ESWIN E302A is a 32-bit RISC-V automotive-grade CPU IP.
Functional safety mechanism such as Parity/ECC and Stack Pointer Monitor (SPM) are added to meet ASIL-B functional safety standards.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state and events of the CPU.
Functional safety mechanism such as Parity/ECC and Stack Pointer Monitor (SPM) are added to meet ASIL-B functional safety standards.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state and events of the CPU.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit E(M)_Zicsr_Zifencei_Zc_Zicond | ||||
| Mode | Machine-mode, User-mode | ||||
| Security | flexible configuration for 0-16 PMP regions | ||||
| Pipeline | 3-stage pipeline | ||||
| TIM | TIM0 and TIM1, with configurable sizes from 0KB to 128MB, and optional Parity/ECC | ||||
| Interrupt | CLIC interrupt controller, supporting up to 112 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module, supporting JTAG/cJTAG | ||||
| Bus Interface | 1. Peripheral Port: 32-bit AHB master interface 2. Front Port: 32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
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| CoreMark（CoreMarks/MHz） | 3.02 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 1.66 | ||||
