Home
> RISC-V Technologies
> RISC-V
CPU
IPs
> RISC-V 32-bit Architecture IPs
>
E320
E320
RISC-V 32-bit Architecture IPs
E320:
ESWIN E320 is a 32-bit RISC-V embedded CPU IP with DSP applications.
Besides RV32IMACB(F) instruction sets, it supports the complete set of RISC-V DSP extension V0.9.11, including 244 instructions of Zpn + Zbpbo + Zpsfoperand.
RISC-V N-Trace can be selected for advanced debugging.
ESWIN Performance Extension is supported.
Besides RV32IMACB(F) instruction sets, it supports the complete set of RISC-V DSP extension V0.9.11, including 244 instructions of Zpn + Zbpbo + Zpsfoperand.
RISC-V N-Trace can be selected for advanced debugging.
ESWIN Performance Extension is supported.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit IMACB(F)(P)_Zicsr_Zifencei_Zicbom | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | supporting Smepmp, and flexible configuration for 0-16 PMP regions | ||||
| Pipeline | 3-stage pipeline | ||||
| TIM | TIM0 and TIM1, with configurable sizes from 0KB to 128MB | ||||
| L1 I$ | configurable sizes from 4KB to 128KB | ||||
| L1 D$ | configurable sizes from 4KB to 128KB | ||||
| Interrupt | CLIC interrupt controller, supporting up to 496 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module: supporting JTAG/cJTAG Trace module: supporting RISC-V N-Trace |
||||
| Bus Interface | 1. ICache Port: 32-bit AHB-Lite master interface 2. Dcache Port: 32-bit AHB-Lite master interface 3. Peripheral Port: 32-bit AHB-Lite master interface 4. Front Port: 32-bit AHB-Lite slave interface |
||||
| CoreMark（CoreMarks/MHz） | 4.10 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 1.98 | ||||
