RISC-V CPU IPs
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E315
E315
RISC-V 32-bit Architecture IPs
E315:
ESWIN E315 is a 32-bit RISC-V embedded CPU IP for general purpose.

On top of E310, E315 has the optional L1 instruction cache and optional L1 data cache, RV32B operation extension, RV32F floating-point extension, and Zicbom cache operation extension.

Meanwhile, it can take either AXI bus or AHB bus for xCache (ICache or Dcache) external interfaces.
E315
Features
Features Description
ISA RISC-V 32-bit IMAC(F)(B)_Zicsr_Zifencei_Zicbom
Modes Machine-mode, User-mode
Security supporting Smepmp, and flexible configuration for 0-16 PMP regions
Optional ESWIN Trusted Execution Environment (TEE) solution with physical memory protection (PMP) regions up to 64
Pipeline 3-stage pipeline
TIM TIM0 and TIM1, with configurable sizes from 0KB to 128MB, Parity/ECC optional
L1 I$ configurable sizes from 4KB to 128KB, Parity/ECC optional
L1 D$ configurable sizes from 4KB to 128KB, Parity/ECC optional
Interrupt CLIC interrupt controller, supporting up to 112 interrupt requests and non-maskable interrupts (NMI)
Debug Debug module, supporting JTAG/cJTAG
Bus Interface 1. ICache Port: 32-bit AHB/AXI master interface
2. DCache Port: 32-bit AHB/AXI master interface
3. The instruction cache interface and the data cache interface can be combined into one system interface
4. Peripheral Port: 32-bit AHB master interface
5. Front Port: 32-bit AHB slave interface, used for external access to TIMs