RISC-V CPU IPs
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E310
E310
RISC-V 32-bit Architecture IPs
E310:
ESWIN E310 is a 32-bit RISC-V embedded CPU IP for general purpose, with the characteristics of low power consumption and high cost performance.

With 32 general-purpose registers, it has better performance.

It has two optional two optional Tightly Coupled Memories (TIM), which can be used for either instructions or data. An external host can access to TIMs through the front door.

Smepmp security extension is supported as well.
E310
Features
Features Description
ISA RISC-V 32-bit IMAC_Zicsr_Zifencei
Modes Machine-mode, User-mode
Security flexible configuration for 0-16 PMP regions
Pipeline 3-stage pipeline
TIM TIM0 and TIM1, with configurable sizes from 0KB to 128MB
Interrupt CLIC interrupt controller, supporting up to 112 interrupt requests and non-maskable interrupts (NMI)
Debug Debug module, supporting JTAG/cJTAG
Bus Interface 1. System Port: 32-bit AHB master interface
2. Peripheral Port: 32-bit AHB master interface
3. Front Port: 32-bit AHB slave interface, used for external access to TIM0 and TIM1