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E310
E310
RISC-V 32-bit Architecture IPs
E310:
ESWIN Computing E310 32-bit general-purpose processor is a 32-bit RISC-V embedded CPU IP product with low power consumption.
With 32 general-purpose registers, it has better performance.
It has two optional tightly coupled memories (TIM), which can be used for either instructions or data. An external host can access to TIMs through the front door. It supports two optional tightly coupled memory (TIM), which can be used to store instructions or data, and supports external host access through the front door.
Smepmp security extension is supported.
With 32 general-purpose registers, it has better performance.
It has two optional tightly coupled memories (TIM), which can be used for either instructions or data. An external host can access to TIMs through the front door. It supports two optional tightly coupled memory (TIM), which can be used to store instructions or data, and supports external host access through the front door.
Smepmp security extension is supported.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit IMAC_Zicsr_Zifencei | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | PMP Region can optional from 0 to 16 | ||||
| Pipeline | 3-stage pipeline | ||||
| TIM | TIM0 and TIM1, with configurable sizes from 0KB to 128MB | ||||
| Interrupt | CLIC interrupt controller, supports 112 interrupt requests and non-maskable interrupt (NMI) | ||||
| Debug | Debug module, supports JTAG/cJTAG | ||||
| Bus Interface | 1. System Port: 32-bit AHB master interface 2. Peripheral Port: 32-bit AHB master interface 3. Front port : 32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
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| CoreMark（CoreMarks/MHz） | 3.58 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 1.59 | ||||
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