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E302
E302
RISC-V 32-bit Architecture IPs
E302:
ESWIN E302 is a 32-bit RISC-V CPU IP for general purpose, with the characteristics of ultra-low power consumption and ultra-high cost performance.
Based on E301, E302 supports RISC-V Zc, Zicond and Smepmp extension to improve code density and security.
In addition, it has two optional Tightly Coupled Memories (TIM), which can be used for either instructions or data. An external master can access to TIMs through the front door.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state, registers and events of the CPU.
Based on E301, E302 supports RISC-V Zc, Zicond and Smepmp extension to improve code density and security.
In addition, it has two optional Tightly Coupled Memories (TIM), which can be used for either instructions or data. An external master can access to TIMs through the front door.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state, registers and events of the CPU.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit E(M)_Zicsr_Zifencei_Zc_Zicond | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | flexible configuration for 0-16 PMP regions | ||||
| Pipeline | 3-stage pipeline | ||||
| TIM | TIM0 and TIM1, with configurable sizes from 0KB to 128MB | ||||
| Interrupt | CLIC interrupt controller, supporting up to 112 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module, supporting JTAG/cJTAG | ||||
| Bus Interface | 1. Peripheral Port: 32-bit AHB master interface 2. Front Port: 32-bit AHB slave interface; used for external access to TIM0 and TIM1 |
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| CoreMark（CoreMarks/MHz） | 3.02 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 1.66 | ||||
