S516-ESWIN Computing

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RISC-V 64-bit Architecture IPs

S516

RISC-V 64-bit Architecture IPs

S516:

ESWIN Computing S516 64-bit AI acceleration processor is a high energy-efficient RISC-V application-level CPU IP product that meets the RVA23-Profile.

Supports Advanced Interrupt Architecture (AIA).

The applicable scenarios include edge computing, smart TVs, set-top boxes, computers, mobile devices, and other intelligent computing domains.

Features

Features		Description
ISA		RVA23+Vector Crypto
Multi-core		Supports up to 8 cores per cluster
Modes		Machine-mode, Hypervisor-mode, Supervisor-mode, User-mode
Security		Supports ESWIN TEE solution, with up to 64 PMP regions
Crypto		Supports optional scalar, vector hardware encryption and decryption module
Vector		Supports RVV1.0, with configurable widths (128-bit, 256-bit, 512-bit, or 1024-bit)
Virtualization		Virtualization - IOMMU +AIA
Pipeline		8-stage superscalar in-order pipeline, 2-way decode
Branch Predictor		L0_BTB, IJTB, NN-Predictor, RAS, Loop Buffer
Prefetch		Supports instruction prefetch, data prefetch
Architecture features		Supports instruction fusion, write streaming mode, partial out-of-order execution
L1 I$		Size is configurable from 8KB to 64KB, ECC optional
L1 D$		Size is configurable from 8KB to 64KB, ECC optional
Cluster LLC		Size is configurable from 256KB to 4MB, ECC optional
MMU		SV39/SV48, ITLB, DTLB Supports hardware self-modifying PTE (Page Table Entry)
Interrupt		APLIC（AIA+PLIC）
Debug		Debug module: supports JTAG Trace module: supports RISC-V standard E-Trace/ N-Trace
Bus Interface		1.Memory Port: 128–bit AXI master interface 2.Peripheral Port: 64-bit AXI master interface 3.Front port : 128-bit AXI slave interface

S516 Data Manual Download

File format: PDF | File size: 1.17 MB

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