RISC-V CPU IPs
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RISC-V 64-bit Architecture IPs
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S516
S516
RISC-V 64-bit Architecture IPs
S516:
S516 is a high energy-efficient 64-bit RISC-V application-grade general-purpose processor that meets the RVA23S-Profile, which supports Advanced Interrupt Architecture (AIA).

The applicable scenarios include ddge computing, smart TVs, set-top boxes, computers, mobile devices, and other intelligent computing domains.
S516
Features
Features Description
ISA RVA23+Vector Crypto
Multi-core single core, dual core, 4 core options
Modes Machine-mode, Hypervisor-mode, Supervisor-mode, User-mode
Security supporting ESWIN TEE solution, with up to 64 PMP regions
Crypto supporting optional scalar, vector hardware encryption and decryption module
Vector supporting RVV1.0, with configurable widths (128-bit, 256-bit, 512-bit, or 1024-bit)
Virtualization Virtualization - IOMMU +AIA
Pipeline 8-stage superscalar in-order pipeline, 2-way decode
Branch Predictor L0_BTB, IJTB, NN-Predictor, RAS, Loop Buffer
Prefetch supporting instruction prefetching and data prefetching
Architecture Features supporting instruction fusion, write streaming mode, partial out-of-order execution
L1 I$ size is configurable from 8KB to 64KB, ECC optional
L1 D$ size is configurable from 8KB to 64KB, ECC optional
Cluster LLC size is configurable from 256KB to 4MB, ECC optional
MMU SV39/SV48, ITLB, DTLB
supporting hardware self-modifying PTE (Page Table Entry)
Interrupt APLIC(AIA+PLIC)
Debug Debug module: supports JTAG
Trace module: supports RISC-V standard E-Trace/ N-Trace
Bus Interface 1. Memory Port: 128–bit AXI master interface
2. Peripheral Port: 64-bit AXI master interface
3. Front Port : 128-bit AXI slave interface