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S500
S500
RISC-V 64-bit Architecture IPs
S500:
ESWIN S500 is an energy-efficient 64-bit Linux capable RISC-V CPU IP.
It adopts self-developed 9-stage pipeline dual issue in order, and supports multicores, and SMP. A core cluster can have up to 4 cores inside.
It enables running Linux and other operating systems that require MMU support.
The trusted execution environment is supported to meet the system security requirements.
The optional E-Trace/N-Trace for advanced debugging function is supported. With the characteristics of high energy efficiency and extensive application fields. It can be applied to AIoT edge computing, network devices and baseband communication, etc.
It adopts self-developed 9-stage pipeline dual issue in order, and supports multicores, and SMP. A core cluster can have up to 4 cores inside.
It enables running Linux and other operating systems that require MMU support.
The trusted execution environment is supported to meet the system security requirements.
The optional E-Trace/N-Trace for advanced debugging function is supported. With the characteristics of high energy efficiency and extensive application fields. It can be applied to AIoT edge computing, network devices and baseband communication, etc.
Features
| Features | Description | ||||
| ISA | RV64 GCB(V) | ||||
| Multi-core | single core, dual core, 4 core option available | ||||
| Modes | Machine-Mode, Supervisor-Mode, User-Mode | ||||
| Security | supporting ESWIN TEE solution, with up to 64 PMP regions | ||||
| Pipeline | 9-stage superscalar in-order pipeline, and 2-way decode | ||||
| Branch Predictor | L0_BTB, BTB, IJTB,BHT, RAS, Loop Buffer | ||||
| L1 I$ | configurable sizes from 8KB to 64KB, ECC optional | ||||
| L1 D$ | configurable sizes from 8KB to 64KB, ECC optional | ||||
| Cluster LLC | configurable sizes (256KB-4MB), ECC optional | ||||
| MMU | SV39, ITLB, DTLB | ||||
| Interrupt | CLINT, PLIC | ||||
| Debug | Debug module, supporting JTAG Trace module, supporting standard E-Trace of RISC-V |
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| Bus Interface | 1. Memory Port: 128–bit AXI master interface 2. Peripheral Port: 128-bit AXI master interface 3. Front Port: 128-bit AXI slave interface |
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| Vector | supporting RVV1.0 | ||||
| CoreMark（CoreMarks/MHz） | 5.80 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 3.15 | ||||
