ESWIN Computing R520A 32-bit functional-safety processor is a high-performance 32-bit RISC-V automotive grade muti-core real-time CPU IP product with ISO-26262 automotive functional safety ASIL-D level certification.

Support the RV32GCBP instruction set, including official extensions such as Zfh (semi precision floating-point), Zicobom (cache operation), Zicond (conditional execution), Zicsr (CSR read and write), Zience (fetch barrier), SmePMP (enhanced address protection), SPMP (supervised mode address protection), SBA (system mainline access), etc.

Support functions such as PPMA (Programmable Address Attribute Check), cache consistency feature Stack Monitor, ESWIN Sight (Internal Signal Insight), N-Trace (Instruction Flow Tracking), etc.

Supports Dual Core LockStep with Split/Lock modes. In Dual Core Lock mode, per two R500A cores in synchronized, enabling fault detection and reporting during system runtime, with error filtering and handling decided by the integrated environment; In Dual Core Split mode, the R500A core can decouple through configuration to independently execute different instruction sequences, improve processing performance, and match more application scenarios.

Supports multiple functional safety mechanisms: bus interface protection, SRAM interface protection, and non-safety module isolation.

It can run various real-time operating systems such as RTOS and μClinux, and is also compatible with Linux operating systems that support SPMP.

Suitable for designs with high requirements for interrupt processing speed, such as industrial control, medical device control, storage device control, modem, 5G communication, streaming media transmission, etc., especially suitable for in vehicle ECU/DCU and automotive grade IC design fields.