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R520A
R520A
RISC-V 32-bit Architecture IPs
R520A:
ESWIN R520A is a 32-bit Real-Time automotive-grade RISC-V CPU IP, with ISO-26262 ASIL-D level automotive functional safety certification.
It supports the RV32GCBP instruction set, including official extensions such as Zfh (semi precision floating-point), Zicobom (cache operation), Zicond (conditional execution), Zicsr (CSR read and write), Zience (fetch barrier), SmePMP (enhanced address protection), SPMP (supervised mode address protection), SBA (system mainline access), etc.
Additional features include PPMA (Programmable Address Attribute Check), Cache prefetch, CCP (Cache Coherent Interface), Stack Monitor, ESWIN Sight (Internal Signal Insight), N-Trace (Instruction Flow Tracking), etc.
R520A supports Dual-Core Lockstep with Split/Lock modes. In Dual-Core Lock mode, the two R500 cores are synchronized and can conduct fault detection and reporting during system runtime, with error filtering and handling decided by the integrated environment. In Dual-Core Split mode, the two R500 c
It supports the RV32GCBP instruction set, including official extensions such as Zfh (semi precision floating-point), Zicobom (cache operation), Zicond (conditional execution), Zicsr (CSR read and write), Zience (fetch barrier), SmePMP (enhanced address protection), SPMP (supervised mode address protection), SBA (system mainline access), etc.
Additional features include PPMA (Programmable Address Attribute Check), Cache prefetch, CCP (Cache Coherent Interface), Stack Monitor, ESWIN Sight (Internal Signal Insight), N-Trace (Instruction Flow Tracking), etc.
R520A supports Dual-Core Lockstep with Split/Lock modes. In Dual-Core Lock mode, the two R500 cores are synchronized and can conduct fault detection and reporting during system runtime, with error filtering and handling decided by the integrated environment. In Dual-Core Split mode, the two R500 c
Features
| Features | Description | ||||
| ISA | RV32 IMA(FD)C(B)(P)_Zicsr_Zifencei_Zicbom_Zicond_(Zfh) | ||||
| Modes | Machine-mode, Supervisor-mode, User-mode | ||||
| Security | configuration up to 16 PMP regions and up to 64 PPMA SPMP regions | ||||
| Pipeline | 6-stage superscalar in-order pipeline,with Branch Predictor | ||||
| ITIM | configurable sizes from 0KB to 128MB, ECC optional | ||||
| DTIM | configurable sizes from 0KB to 128MB, ECC optional | ||||
| L1 I$ | configurable sizes from 4KB to 128KB, ECC optional | ||||
| L1 D$ | configurable sizes from 4KB to 128KB, ECC optional | ||||
| FPU | supporting RISC-V Zfh half-precision, single-precision and double-precision floating-point | ||||
| DSP | supporting full RV32P | ||||
| Interrupt | CLIC interrupt controller, supports up to 1008 fast interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module: supports JTAG/cJTAG and SBA（System Bus Access Port) Trace module: supports RISC-V N-Trace |
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| Bus Interface | 1. Memory Port: 64-bit AXI master interface 2. Peripheral Port: 32-bit AHB master interface 3. Front Port: 64-bit AXI slave interface, used for external access to ITIM and DTIM |
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| CoreMark（CoreMarks/MHz） | 5.26 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 2.89 | ||||
