| Features | Description | ||||
| ISA | RISC-V 32-bit IMAC(B)(FD)(P)(K)_Zicsr_Zifencei_Zicbom_Zicond_Zilsd_xewcie | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | Supports Smepmp, PMP Region can optional from 0 to 16 Supports PPMA (Programmable Physical Memory Attributes) check |
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| Pipeline | 6-stage superscalar in-order pipeline, with Branch Predictor | ||||
| TIM | ITIM and DTIM, with configurable sizes from 0KB to 128MB | ||||
| L1 I$ | Size configurable from 4KB to 128KB | ||||
| L1 D$ | Size configurable from 4KB to 128KB | ||||
| Interrupt | CLIC interrupt controller, supports 496 interrupt requests and non-maskable interrupt (NMI) | ||||
| Debug | Debug module: supports JTAG/cJTAG Trace module: supports RISC-V N-Trace |
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| Bus Interface | 1. Memory Port:64-bit AHB/AXI master interface 2. Peripheral Port:32-bit AHB master interface 3. Front port:32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
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| CoreMark(CoreMarks/MHz) | 5.77 | ||||
| Dhrystone-Legla(DMIPS/MHz) | 2.48 | ||||