E330-ESWIN Computing

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RISC-V 32-bit Architecture IPs

E330

RISC-V 32-bit Architecture IPs

E330:

ESWIN Computing E330 32-bit general-purpose processor is a 32-bit RISC-V embedded CPU IP product with high-performance.It supports RV32 IMACB (FD)(P)(K) instruction set, as well as Zicond conditional execution extension, Ziccom cache operation extension, Smepmp security extension, Zilsd extension and CIE coprocessor interface extension.

To ease user RTL simulation debugging, it provides an ESWIN Sight function to let users easily probe the internal state and events of the CPU.

E330 is superscalar 6-stage pipeline architect with branch predictor inside. Its performance can meet a wide range of high-performance embedded applications.

Features

Features		Description
ISA		RISC-V 32-bit IMAC(B)(FD)(P)(K)_Zicsr_Zifencei_Zicbom_Zicond_Zilsd_xewcie
Modes		Machine-mode, User-mode
Security		Supports Smepmp, PMP Region can optional from 0 to 16 Supports PPMA (Programmable Physical Memory Attributes) check
Pipeline		6-stage superscalar in-order pipeline, with Branch Predictor
TIM		ITIM and DTIM, with configurable sizes from 0KB to 128MB
L1 I$		Size configurable from 4KB to 128KB
L1 D$		Size configurable from 4KB to 128KB
Interrupt		CLIC interrupt controller, supports 496 interrupt requests and non-maskable interrupt (NMI)
Debug		Debug module: supports JTAG/cJTAG Trace module: supports RISC-V N-Trace
Bus Interface		1. Memory Port:64-bit AHB/AXI master interface 2. Peripheral Port:32-bit AHB master interface 3. Front port:32-bit AHB slave interface, used for external access to TIM0 and TIM1
CoreMark（CoreMarks/MHz）		5.77
Dhrystone-Legla（DMIPS/MHz）		2.48

E330 Data Manual Download

File format: PDF | File size: 1.02 MB

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