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E330
E330
RISC-V 32-bit Architecture IPs
E330:
ESWIN E330 is an energy-efficient 32-bit RISC-V embedded CPU IP for general purpose.
The RISC-V 32 IMA(FD)CB(P) instruction set, the Zicond conditional execution extension, Zicbom cache operation extension and Smepmp security extension are supported.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state and events of the CPU.
E330 is superscalar 6-stage pipeline arichitect with branch predictor inside, which can be applied to a wide range of high-performance embedded applications.
The RISC-V 32 IMA(FD)CB(P) instruction set, the Zicond conditional execution extension, Zicbom cache operation extension and Smepmp security extension are supported.
To make it easier for users to debug RTL simulations, ESWIN Sight function is provided to easily probe the internal state and events of the CPU.
E330 is superscalar 6-stage pipeline arichitect with branch predictor inside, which can be applied to a wide range of high-performance embedded applications.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit IMA(FD)CB(P)_Zicsr_Zifencei_Zicbom_(Zicond) | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | supporting Smepmp, and flexible configuration for 0-16 PMP regions | ||||
| Pipeline | 6-stage superscalar in-order pipeline, with Branch Predictor | ||||
| TIM | ITIM and DTIM, with configurable sizes from 0KB to 128MB | ||||
| L1 I$ | configurable sizes from 4KB to 128KB | ||||
| L1 D$ | configurable sizes from 4KB to 128KB | ||||
| Interrupt | CLIC interrupt controller, supporting up to 496 interrupt requests and non-maskable interrupts (NMI) | ||||
| Debug | Debug module: supports JTAG/cJTAG Trace module: supports RISC-V N-Trace |
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| Bus Interface | 1. Memory Port: 64-bit AHB/AXI master interface 2. Peripheral Port: 32-bit AHB master interface 3. Front Port: 32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
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